NSF AI grant $1.13M: "photonic AI computing" that cuts AI energy use by orders of magnitude (UC Berkeley / NSF-Intel)
The NSF awarded about $1.13M to research a photonic-electronic hybrid processor that performs AI matrix operations with light, aiming to cut energy use by up to two orders of magnitude versus CMOS. Using wafer-scale heterogeneous integration of thin-film lithium niobate (TFLN) and silicon, it would support real-time decisions for LLMs and multi-agent systems at low energy.
Grant overview (primary data)
- Award amount$1,130,000 / Est. total $1,490,000
- RecipientUniversity of California-Berkeley(CA)
- ProgramNSF-Intel Semiconductr Partnrs, ASCENT-Address-Chalg-Eng-Teams
- Period2025-10-01 〜 2029-09-30
- FunderU.S. National Science Foundation (NSF) / NSF
Key points
- Performs AI operations with light (photonics), cutting energy by up to two orders of magnitude versus CMOS
- Wafer-scale heterogeneous integration of thin-film lithium niobate (TFLN) and silicon, targeting >100 TOPS/W
- Hyperdimensional photonic circuits, CMOS-compatible high-speed modulators, hardware-software co-design
- Supports real-time decisions for LLMs and multi-agent systems (benchmarked on RL for autonomous driving)
- About $1.13M, led by UC Berkeley, NSF-Intel semiconductor partnership, 2025–2029
The NSF awarded about $1,130,000 to UC Berkeley's "ASCENT: Wafer-scale Heterogeneous Integration of Lithium-Niobate-on-Silicon Optoelectronics for Ultralow-energy AI computing" (NSF Award 2520253; program: NSF-Intel semiconductor partnership / ASCENT; October 2025 – September 2029).
Per the abstract, the increasing data volumes from AI, the internet of things, and 5G/6G networks are challenging the processing power of CMOS-based computing hardware. To extend computing power scaling and energy efficiency, the project proposes light-based photonic integrated computing circuits for high-clock-rate computing with ultralow-loss on-chip data movement. It could significantly reduce the energy required for AI computations — potentially two orders of magnitude (about 100×) more efficient than current CMOS — paving the way for powerful, sustainable computing. Outcomes could affect applications from autonomous vehicles and healthcare diagnostics to natural language processing and scientific discovery, strengthen U.S. competitiveness in semiconductor manufacturing, and train experts in chip design, photonics, and AI.
Technically, it aims to build high-efficiency (>100 TOPS/W), high-throughput photonic-electronic hybrid processors via wafer-scale heterogeneous integration of thin-film lithium niobate (TFLN) and silicon photonics/electronics. Key goals: (1) space-time-wavelength hyperdimensional photonic circuits for massively parallel tensor computation using time-multiplexed encoding; (2) CMOS-compatible high-speed electro-optic modulators with TFLN on silicon (>50 GHz bandwidth, <10 fJ/conversion); and (3) hardware-software co-design to support large models like LLMs and real-time decision-making in multi-agent systems. The architecture achieves matrix multiplications with O(N) modulator scaling, benchmarked end-to-end on reinforcement learning for autonomous driving.
Why it matters
As AI power consumption becomes an issue, an example of hardware research to make "AI computation itself" energy-efficient. A useful read on U.S. research direction for those tracking photonics, semiconductors, and low-power AI (AI data-center power).
FAQ
Why compute "with light"?
How much energy could it save?
Sources (primary)
Source: NSF Award Search (U.S. National Science Foundation, public domain). Amounts are the obligated amount. For privacy, we do not handle principal investigator names.
- NSF Award (original, official)
- NSF Award ID: 2520253